Interconnection Network Switch Architectures and Combining Strategies 1

We have studied a variety of switch architectures for use in the multistage interconnection network of a shared memory multiprocessor. In this paper, we describe a taxonomy of buffered switch architectures and give performance results for the different types we have defined. We investigate two techniques for improving network performance in the presence of contention: the use of multiple handshaking signals and the use of message combining. Simulations results are provided for implementation alternatives using switches of varying capabilities, in order to compare the effectiveness of different methods as system size grows. We show that a practical combining switch design, the two-and-a-half-way combining switch, provides performance as good as other more expensive designs.